Direct Sequence Spread Spectrum (DSSS) modulation is used in a wide variety of applications, including Global Navigation Satellite Systems (GNSS), radio frequency ranging systems, radio frequency time transfer systems, anti-jamming receivers and channel sounding. A DSSS signal comprises a carrier wave that has been phase-modulated with a sequence of pseudonoise “chips”, each chip having a much shorter duration than an information bit. The sequence of chips can be referred to as a spreading code. The information signal can be recovered from a received DSSS signal by multiplying the received DSSS signal with a replica of the spreading code. This demodulation process requires the replica spreading code to be accurately aligned in frequency and phase with the received DSSS signal.
To demodulate a received DSSS signal, a two-stage process is used. The first stage is acquisition, this involves establishing an initial estimation of the received spread signal frequency and the code phase. The initial estimates allow the replica spreading code to be aligned to within ±1 code chip. Then in the second stage, carrier tracking, the replica spreading code phase is more accurately synchronised to the received code phase to despread the received DSSS signal, and a Frequency Lock Loop (FLL) and Phase Lock Loop (PLL) accurately track the frequency and phase of the de-spread signal.
A conventional code tracking implementation is shown in FIG. 1, and includes a Delay Lock Loop (DLL) which performs correlations of the input signals with early (by a fraction of a chip), prompt (on time) and late (by a fraction of a chip) versions of the replica spreading code. In detail, as shown in FIG. 1, the code tracking apparatus receives an intermediate frequency (IF) signal, which is a down-converted received DSSS signal. The IF signal is mixed with sine and cosine waveforms generated by a carrier Numerically Controlled Oscillator (NCO) 101 to generate In-phase (I) and Quadrature (Q) components. The I and Q components are each correlated with the Early (E), Prompt (P), and Late (L) versions of the replica spreading code, generated by a code generator 102, and passed through Integrate and Dump (I&D) filters.
A DLL discriminator 103 outputs an error signal corresponding to the difference between the early and late correlator outputs, which gives an indicator of the loop error. The error signal is passed through a code filter 104 and used to drive the code generator 102 appropriately to synchronise the received signal with the replica code sequence.
Separate tracking loops are implemented in the time domain to track carrier frequency and phase which is required for data demodulation. In this example the loop discriminator is based on an ATAN function 105 and uses the prompt correlator as its input. The output of the ATAN function 105 is filtered in a carrier loop filter 106 and fed back to control the carrier NCO 101. A drawback of this design is that the code and carrier loops are tightly coupled, since the output of the DLL discriminator 103 in the code loop will be affected by changes in the carrier NCO frequency and phase caused by operation of the carrier loop.
Other drawbacks of the conventional code tracking approach include the requirement for a separate dedicated DLL, with associated frequency and phase tracking loops, per signal source to be tracked. Also, DLL operation is generally based on discriminators which operate on signal envelopes or powers, with the result that the loop action is a non-coherent averaging process.
In addition, modern satellite navigation signals are using more complex navigation signal formats, for example the Galileo System uses binary offset coding (BOC). For these waveform types a conventional DLL tracking loop as shown in FIG. 1 can also suffer from false lock due to tracking on a correlation side lobe, as well as impaired tracking accuracy in the presence of multipath interference.
The invention is made in this context.